Recently, many reactance-less memristive relaxation oscillators were introduced, where the charging and discharging processes depend on memristors. In this paper, we investigate the power dissipation in different memristor based relaxation oscillators. General expressions for these memristive circuits as well as the power dissipation formulas for three different topologies are derived analytically. In addition, general expressions for the maximum and minimum power dissipation are calculated. Finally, the calculated expressions are verified using PSPICE simulations showing very good matching.

Recently, the applications of memristors have spread into many fields and especially in the circuit theory. Many models have been proposed for the HP-memristor based on the window functions. In this paper, we introduce a complete mathematical analysis of the controlled reactance-less oscillator for two different window functions of Joglekar's model (linear and nonlinear dopant drift) to discuss the effect of changing the window function on the oscillator's behavior. The generalized necessary and sufficient conditions based on the circuit elements and control voltages for both the linear and

Memristors are used in many innovative research areas. However, the temperature has a strong effect on mem-ristance, which results in malfunctions. Although commercial a memristor is available, its thermal characteristics are still under-explored. This paper presents a temperature model of a self-directed channel memristor. The experimental results of measuring high-resistive-state memristance between 253K and 383K show the inverse relation, which can be described by an exponential equation. This relation is similar to metal-oxide memristors; therefore, our model is expected to cover many

This paper introduces a mathematical model of an ideally threshold compensated rectifier for RF energy harvesting. The ideally compensation arrangement has been exploited to improve the rectifier's performance and overcome the limitation of rectifier's sensitivity which mainly depends on the threshold voltage of the rectifying devices (transistors). The model considers the conduction angle and the reverse current in deriving closed form analytical expressions for output dc voltage and efficiency. Using a 65-nm low leakage CMOS process with low-threshold transistors, 900-MHz multi-stages

Measuring phase noise in oscillators is crucial in communication systems, vibration analysis, and frequency synthesizers. Traditionally, this measurement is done in frequency domain by estimating the ratio of the power density at an offset frequency from the carrier to the power of the carrier signal. This approach is hardware intensive and dependent on the the offset frequency, for which there exists no standard. Here, we propose an alternative method to quantify phase noise but in the time domain in the form of a root-mean-square true phase angle deviation. This is done using a self-created

We propose a mathematical system capable of exhibiting chaos with a chaotic attractor which is odd symmetrical in the x − y phase plane but even symmetrical in the x − z and y − z phase planes respectively. A hardware implementation of the system is done on a digital FPGA platform for verification. The system is also attractive in the sense that (i) its dynamics are single-parameter controlled and (ii) it inherently generates two chaotic clock signals. As an application, an FPGA design methodology using this oscillator for speech encryption is demonstrated. The security of the proposed

In this study, we report the electrical response of two sets of solid-state fractional-order electrochemical capacitors for which the low-frequency impedance phase angle can be tuned from - 69 ° to - 7 °. The configuration makes use of a gel electrolyte in which carbonaceous additives (graphite or reduced graphene oxide) are dispersed at different proportions. Such a disordered electrolyte structure results in subdiffusive charge transport and thus a frequency dispersive capacitive-resistive behavior typical of a constant phase element, which can be useful for both frequency applications and

To implement an approximation of the fractional order Laplacian operator s α as a weighted sum of high pass filter sections, it is essential to extract the cutoff frequencies and filter gains of each section in order to achieve the lowest error possible. Therefore, in this work, five meta-heuristic optimization algorithms are tested in this problem based on a weighted sum objective function. The employed algorithms include the: ant-lion optimizer, cuckoo search algorithm, flower pollination algorithm, whale optimizer, and multi-verse algorithm. A comparison is carried out between the results

A new second-order MOS transistor based circuit block approximating the behavior of a fractional-order capacitor is proposed. The circuit is modular and therefore the order of the approximation can be increased by more stages of the same circuit in cascade or in parallel. Simulation results using a TSMC 65nm CMOS technology are provided and show less than 2o of phase error in two decades around the center frequency of the approximation. Experimental results of realized fractional-order capacitors and of a fractional-order relaxation oscillator are also shown. © 2019 IEEE

Shared by various physical, chemical, and biological systems, fractional-order dynamics assert that the present state of a system is the result of not only the applied stimulus but also its past history. Consequently, in fractional-order systems, there exists a system-specific, input-dependent memory kernel. In this study, we demonstrate experimentally the existence of a memory effect in electric double-layer capacitors which are known to exhibit a fractional-order behavior through their non-single, distributed internal time constants. This is performed by showing variance in the discharge