As on-chip integration increases, the thermal distribution becomes spatially non-uniform and varies based on the power dissipation. In this paper, we introduce a temperature-aware task-mapping algorithm to prevent hotspots and achieve a highly uniform thermal distribution using adaptive multi-threshold values. The algorithm monitors the temperature of the cores, swaps tasks when the temperature of the core is relatively higher than the average temperature of the chip. Cores are switched off if they exceed an absolute maximum temperature. Using this algorithm, reliability is enhanced by

This paper presents an improved memristor-based relaxation oscillator which offers higher frequency and wider tunning range than the existing reactance-less oscillators. It also has the capability of operating on two positive supplies or alternatively a positive and negative supply. Furthermore, it has the advantage that it can be fully integrated on-chip providing an area-efficient solution. On the other hand, The oscillation concept is discussed then a complete mathematical analysis of the proposed oscillator is introduced. Furthermore, the power consumption of the new relaxation circuit is

This paper proposes two generalized topologies of fractional order inverse filters (FOIF). All possible realizations of each topology are investigated using the second generation current conveyor (CCII) family. Inverse fractional highpass (IFHPF), inverse fractional bandpass (IFBPF), and inverse fractional lowpass (IFLPF) filters are realized using the same topology based on the generalized admittances. Numerical and P-Spice simulation results are presented for selected cases to approve the theoretical findings. The fractional order parameters increase the design flexibility and

Supercapacitors are commonly viewed and mainly employed as dc electrical energy storage devices. Their behavior at far-from-dc is usually overlooked and not well explored for potential applications. In this work, we investigate analytically and experimentally the performance of supercapacitor at high frequencies, including the 50 Hz/60 Hz power line frequencies. The variation of effective capacitance, power and energy with frequency are analyzed using a fractional-order model consisting of a series resistance and a constant phase element for both pure sinusoidal and full-wave rectified voltage

Bipolar electrochemistry is used as an economical, single-step, and scalable process for the oxidation of a wireless graphite substrate, and the subsequent electrophoretic deposition of graphene oxide thin film on a second wireless substrate. An all-solid-state symmetric double-layer capacitor (EDLC) using binderless reduced graphene oxide electrodes exhibited outstanding reversibility and capacitance retention over 18000 cycles, as well as superior capacitive behavior at far-from-dc frequencies (for example 45 and 47 µ F cm-2), effective capacitances at 75 and 189 Hz, respectively (computed

In this paper, a power-aware process variation calibration scheme is proposed. The proposed calibration system provides the ability to detect and control the n- and p-type variations independently through the use of all-n and all-p ring oscillators. Calibration is then carried out through the use of the supply voltage and body bias to alter the device parameters to match those of a certain process corner that is determined by the system designer. This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load. The calibration

A process and temperature variation calibration scheme is proposed in this paper. The proposed system uses the supply voltage and body bias to calibrate the device parameters to match those of a certain process corner that is determined by the system designer. This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load. Moreover, the proposed system provides the ability to detect and control the n- and p-type variations independently through the use of an all-n and all-p ring oscillators. The calibration system has been

Power reduction is the main challenge facing circuit designers in their quest to utilize the full performance of new process technologies. A major portion of the power consumed in today's systems is due to the clock generation and distribution. Resonant clocking has been a promising technique to reduce the clock power dramatically. In this paper, a novel resonant clock generator circuit is proposed to reduce the dynamic power used for clock generation by almost 75%. Two configurations of the circuit are presented. The merit of this generator is most obvious in the ease of its implementation

Supercapacitors are typically used in applications requiring frequent and continuous charging/discharging cycles, but most of the models available in the literature are designed to predict their behavior for a single sequence. In this letter, we show first that the electrical response and metrics of supercapacitors under periodic voltage excitations can generally be obtained using Fourier series analysis and convolution operations of functions derived based on any suitable impedance model. We verified our analysis procedure with simulations using particle swarm optimization, and experiments

The power-energy performance of supercapacitors is usually visualized by the Ragone plot of (gravimetric or volumetric) energy density vs power density. The energy is commonly computed from E = CV2/2, and the power from P = E/Δt, which assume RCbased models. In this study, we investigate the energy-power profiles of two commercial supercapacitors discharged with three different types of loads: (i) constant current, (ii) constant power, and (iii) constant resistive load. The energy is computed as per the definition from the time-integral of its instantaneous power, i.e. E(t) = ò p(t)dt with p(t