In this paper, the series and parallel connections of the fractional flux-controlled memristors are studied. Asymmetric I-V hysteresis with high I-V nonlinearity can be obtained from single fractional memristor as reported in literature. However, connecting different memristor emulators can convert the asymmetric hysteresis to symmetric one and maintaining the high I-V nonlinearity to be used in

The need for portable and low-cost bio-impedance analyzers that can be deployed in field studies has significantly increased. Due to size and power constraints, reducing the hardware in these devices is crucial and most importantly is removing the need for direct phase measurement. In this paper a new magnitude-only technique based on modified Kramers–Kronig transforms is proposed and tested

Supercapacitors are commonly viewed and mainly employed as dc electrical energy storage devices. Their behavior at far-from-dc is usually overlooked and not well explored for potential applications. In this work, we investigate analytically and experimentally the performance of supercapacitor at high frequencies, including the 50 Hz/60 Hz power line frequencies. The variation of effective

This paper presents a complete analysis of the mathematical model of the gene regulation process. The model describes the induced gene expression under the effect of activators. The model differential equations are solved analytically, and the exact solution of the gene model is introduced. Moreover, a study of the model dynamics, including the fixed points and stability conditions are presented

This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related

This paper proposes a speech encryption and decryption system, its hardware architecture design and FPGA implementation. The system utilizes Nosé Hoover chaotic generator and/or dynamic shift and bit permutation. The effect of different blocks in the proposed encryption scheme is studied and the security of the system is validated through perceptual and statistical tests. The complete encryption

A fractional-order capacitor and inductor emulator, implemented using MOS transistors, instead of passive capacitors, is introduced in this paper. This is achieved using current mirrors as active elements, without passive resistors, and therefore reducing the circuit complexity and resulting in both a resistorless and capacitorless topology. The emulator has been designed by combining fractional

Nonlinear dynamical systems with chaotic attractors have many engineering applications such as dynamical models or pseudo-random number generators. Discovering systems with hidden attractors has recently received considerable attention because they can lead to unexpected responses to perturbations. In this chapter, several recent examples of hidden attractors, which are classified into several

This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept. Values of the proposed S-Box are different for each sample depending on the behavior of a memristor-based chaotic system. MATLAB simulations and FPGA implementation for the circuit are presented with throughput 4.266 Gbit/s. Also, FPGA realization for encryption/decryption scheme is proposed

This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used