This paper posits an automatic handling to some of the most common RTL critical issues in the verification process. In this paper, we propose an automatic linting tool to handle some causes of intentional latches generated in the synthesis process and clock gating timing violation. Therefore, no need to waste verification time to dive through long codes to handle them manually. The proposed tool

Supercapacitors are electrochemical devices that can store and restore electrical energy and are mostly used for powering dc or close-to-dc applications. As such they have not been explored enough for non-dc circuits. In this study, we implement a band-pass for frequency selectivity purposes and a relaxation oscillator for timing applications using a solid-state carbon electric double-layer

This paper presents two general topologies of fractional order oscillators. They employ Current Feedback Op-Amp (CFOA) and RC networks. Two RC networks are investigated for each presented topology. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are investigated in terms of the fractional order parameters. Numerical simulations and P-Spice

This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit. Grunwald-Letnikov's (GL) definition is used to generalize the chaotic system equations into the fractional-order domain. Xilinx ISE 14.5 is used to simulate the proposed design and Artix-7 XC7A100T FPGA is used for system realization. Experimental results are presented on digital

We propose and validate a simple 3-transistor MOS circuit that shows an all-positive pinched hysteresis behavior. Complete analysis of the circuit is provided along with experimental results using a commercial CMOS transistor array. Copyright © 2018 John Wiley & Sons, Ltd.

A novel topology for implementing fractional-order differentiator and integrator transfer functions is presented in this paper. This topology is based on the employment of a second generation Current Conveyor with EXtra inputs (EX-CCII), passive resistors, and fractional-order capacitors. The main benefit offered by this implementation is that both fractional-order differentiator and integrator

This paper introduces high-speed FPGA implementations of two different chaotic systems that rely on a switching-type nonlinearity. In particular, the single-switch Jerk system and the two-wing butterfly system (previously implemented only in analog form) are realized on a modular FPGA platform. For each system, two different hardware architectures are described: a parameters-independent

The fractional-order derivative and integral of Grünwald Letnikov's definition are implemented based on FPGA for different fractional orders. A new algorithm is proposed to implement the GL integral based on linear approximation approach, where the memory dependency of the fractional order systems is eliminated. Moreover, the linear approximation design shows an improvement of 91% and 92% in the

A new approximation method of the fractional-order Laplacian operator sα is introduced. The approximation is based on a weighted sum of first-order filter sections and its analytical proof is given. The optimal high-pass filter section parameters that cover six frequency decades are obtained using the flower pollination algorithm while the effect of the number of filter sections on the accuracy of

Recently, the triple-lobe behavior is found in the I-V characteristics of some memristive devices generating another non-zero pinchoff point. In this paper, a flux-controlled memristive model is developed to generate the triple-lobe behavior (double pinchoff points) based on a fractional second-order model. The conditions for observing triple lobes are derived besides the coordinates of the