Breadcrumb

A novel high throughput high resolution two-stage oscillator-based TDC
This paper presents a new technique to reduce the conversion time, hence improve the throughput, of the two-stage Time to Digital Converter (TDC) architecture. An oscillator based TDC is used in the first and second stages. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of phase-shift between two oscillating signals. A throughput of 400 MS/s, a DNL of 0.38, and an INL of 0.36 are achieved. © 2013 IEEE.

Spectral current-voltage analysis of kesterite solar cells
Current-voltage analysis using different optical band pass filters has been performed on Cu2ZnSnSe4 and Cu2ZnSn(S,Se) 4 thin-film solar cells. When using red or orange light (i.e. wavelengths above 600 nm), a distortion appears in the I-V curve of the Cu 2ZnSnSe4 solar cell, indicating an additional potential barrier to the current flow in the device for these conditions of illumination. This barrier is reduced when using a Cu2ZnSn(S,Se)4 absorber. Numerical simulations demonstrate that the barrier visible under red light could be explained by a positive conduction band offset at the front

On the mathematical modeling of memcapacitor bridge synapses
Mem-element based synaptic bridge is very promising topic due to its learning capability where the synaptic bridge can be build using either memristors or memcapacitors. In this paper, the detailed mathematical analysis of memcapacitor bridge circuit is introduced. This mathematical analysis is build when a current input signal is applied to excite the bridge. Closed form expressions for the required pulse width; synaptic weight; and conditions for positive, negative and zero synaptic weight are derived. The obtained expressions are verified using SPICE simulations showing very good matching.

A 2.5 μwatts two stage wake-up receiver for Wireless Sensor Networks
An ultra low power wake-up receiver for Wireless Sensor Network (WSN) applications is presented. The proposed wake-up receiver is composed of two stages. The first stage is a low-power low-sensitivity stage that acts as a 'sentinel' and continuously monitors the channel, while the second stage is a conventional low-power wake-up receiver. The 2.44GHz two-stage receiver has a sensitivity of -72dBm when the transmitted signal power is 0dBm. The power consumed during sleep mode is 2.5μWatts and 41μWatts in the wake-up receiver active mode with a 0.5V supply voltage. The power consumption is

Generalized hardware post-processing technique for chaos-based pseudorandom number generators
This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput

The modified single input Op-Amps memristor based oscillator
This paper introduces the modified single input Op-Amps memristor based oscillator. The oscillator is realized with ideal, LM741 and current feedback (AD844) Op-Amps where memristors replace resistors. The effect of memristor on the oscillation frequency and the oscillation condition that are totally independent is studied. This helped in studying the whole operation regime of the memristor. The effect of initial conditions on the circuit behavior is discussed. The dynamic poles of the oscillator after resistors replacement are illustrated. Sustained oscillation is obtained and simulated

Design methodology for square wave resonant clock generators
Resonant clocking is a promising low power alternative for conventional clocking method. In this work, a design methodology is presented for square wave resonant clocking technique to assure minimum power consumption. These equations were verified by designing a differential clock generator which showed 55% power savings compared to conventional clocking. © 2012 IEEE.

On the accuracy of commonly used loss models in SCVRs
[No abstract available]

Image encryption in the fractional-order domain
This paper presents a new image encryption scheme based on the fractional-order Lorenz system which gives more degrees of freedom in key generation. In the modified fractional-order system, the key length is doubled using the three fractional-orde r parameters beside the three initial conditions, which makes it invulnerable to brute-force attacks. In addition, using a very simple algorithm, based on pixel confusion only, strongly encrypted images are produced. Such an algorithm can be used in real time applications. To evaluate the algorithm and analyze the encryption results, a standard image
Pagination
- Previous page ‹‹
- Page 15
- Next page ››