Exploring the implementation of fractional calculus is essential to be adequately used in several applications. This paper introduces an FPGA design methodology of fractional order multi-scrolls chaotic system. Hardware resources comparison proves the efficiency of the proposed method. The designs are simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx Artix 7. Different interesting attractors are realized under various parametric changes with distinct step sizes for different fractional-orders. To verify the proposed fractional order multi-scrolls chaotic system on FPGA, experimental

This paper presents the design of the generalized Double Humped (DH) logistic map, used for pseudo-random number key generation (PRNG). The generalized parameter added to the map provides more control on the map chaotic range. A new special map with a zooming effect of the bifurcation diagram is obtained by manipulating the generalization parameter value. The dynamic behavior of the generalized map is analyzed, including the study of the fixed points and stability ranges, Lyapunov exponent, and the complete bifurcation diagram. The option of designing any specific map is made possible through

This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain. The generalization process involves replacement of three integer-order capacitors with fractional-order ones. The employment of fractional-order capacitors allows a complete tunability of oscillator frequency and phase. The presented oscillators are implemented with three active building blocks which are op-Amp, current feedback operational amplifier (CFOA) and second generation current conveyor (CCII). The general state matrix, oscillation frequency and condition are

This paper presents a generalized family of fractional-order oscillators based on single CFOA and RC network. Five RC networks are investigated with their general state matrix, and design equations. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are introduced in terms of the fractional order parameters. They add extra degrees of freedom which in turn increase the design flexibility and controllability that is proved numerically. Spice simulations are introduced to validate the theoretical findings. © 2017 IEEE.

This paper presents a novel lossless image encryption algorithm based on edge detection and generalized chaotic maps for key generation. Generalized chaotic maps, including the fractional-order, the delayed, and the Double-Humped logistic maps, are used to design the pseudo-random number key generator. The generalization parameters add extra degrees of freedom to the system and increase the keyspace achieving more secure keys. Fractional order edge detection filters exhibited better noise robustness than the conventional integer-order ones, rendering the system to be suitable for medical

This paper proposes a reliable and scalable architecture for firmware-over-the-air updates, which provides remote cloud real-time distribution of new firmware versions on industrial machines in an efficient simultaneous manner. The architecture comprises remotely interconnected software and hardware systems for handling the procedures of firmware distribution over a wireless network. The main contributions are developing a special boot-loader for ARM micro-controllers and an Android application for performing FOTA updates. A simulation is performed using Web and Android applications showing

In this paper, the effect of the fruits aging on bio-impedance is experimentally studied. Bio-impedance analysis, as accurate and fast method is used to investigate and monitor group of apples properties during aging. This method provides an alternative method for investigating apples physical properties that are highly related to chemical properties. AD5933 impedance analyzer chip within the frequency range (5 KHz-100 KHz) and NI-ELVIS board within the frequency range (300 Hz-5 KHz) are used to investigate the changes in apple's properties during aging. According to experimental results, the

In this study we quantify and interpret the inherent memory in fractional-order capacitors when subjected to constant current charging/discharging waveforms. This is done via a finite difference approximation of the fractional order rate equation I(t) = Cαdαv(t)/dtα (0 le; α ≤ 1) relating current to voltage in these devices. It is found that as the fractional exponent α decreases, the weight of the voltage memory trace that results from the contribution of past voltage activity increases, and thus the measured response of the device at any time is increasingly correlated to its past. Ideal

A novel scheme suitable for the emulation of fractional-order capacitors and inductors of any order less than 2 is presented in this work. Classically, fractional-order impedances are characterized in the frequency domain by a fractional-order Laplacian of the form s± α with an order 0 < α< 1. The ideal inductor and capacitor correspond, respectively, to setting α= ± 1. In the range 1 < α< 2 , fractional-order impedances can still be obtained before turning into a Frequency- Dependent Negative Resistor (FDNR) at α= ± 2. Here, we propose an electronically tunable fractional-order impedance

In this letter, a third-order wideband voltage-mode all-pass filter (APF) is proposed for application as a true time delay (TTD) cell. The advantages of designing a single-stage higher order filter over cascading several lower order stages are illustrated. The proposed APF circuit is based on a single metal-oxide-semiconductor (MOS) transistor and is canonical because it requires one resistor, one inductor, and two capacitors. To the best of the authors' knowledge, this is the first single-transistor third-order APF circuit to be reported in the literature. The operation of the proposed APF is